This invention relates to a time base correction apparatus which compensates time axis fluctuations of a video signal.
When a reproduced video signal has a time base error, this error can be compensated by digitalizing the video signal by means of a clock signal having the same time base error and writing the digitalized results in a memory, and reading out the signal by means of a clock signal having no time base error.
FIG. 1 shows an example of conventional time base correction apparatus. A video signal reproduced by a video tape recorder etc., is converted into a digital signal by an A/D converter 11 on the basis of a write clock signal which follows up the time base fluctuations and then stored in a memory 12. Then, based on a read clock signal having no time base fluctuation the digital signal is read out of the memory 12 and, after that, converted into an analog signal by a D/A converter 13 so that the video signal, whose time base error is compensated, can be output.
The write clock signal which follows up time base fluctuations can be generated as follows: A synchronizing separation circuit 14 separates a horizontal synchronizing signal from the reproduced video signal and sends it into a phase locked loop circuit (PLL) 15. The PLL 15 comprises a phase comparator 16, a low pass filter (LPF) 17, a voltage controlled oscillator (VCO) 18, and a divider 19. The VCO 18 sends out a write clock signal that has the same time base fluctuations as that of the horizontal synchronizing signal.
The read clock signal having no time base fluctuation is generated, for example, by an oscillator (OSC) 21 having a fixed oscillation frequency.
Based on the write and read clock signals, memory control circuits 20 and 21, respectively, control read-out from and write in to the memory 12.
FIG. 2 represents another example of conventional time base correction apparatus. This example differs from that in FIG. 1 only in the part of write clock signal generation, and therefore only this part is explained below. That is, the oscillator 21 is used also to generate the write clock signal, which is in turn supplied into a phase control circuit 23 together with the horizontal synchronizing signal fed from the synchronizing signal separation circuit 14. The phase control circuit 23 supplies the clock signal fed from the oscillator 21, for example, to a multiple-stage delay circuit of a small delay time and sends out, from the multiple delay circuit, the signal having the nearest phase to that of the horizontal synchronizing signal among its outputs, as a write clock signal. Therefore, the write clock signal has the same time base fluctuations as that of the horizontal synchronous signal.
In the system shown in FIGS. 1 and 2, the time base error of the reproduced video signal is automatically compensated. However the compensation is limited to components of relatively low frequencies, for example, due to the LPF 17 of FIG. 1. When displayed on the monitor screen the image will more fluctuate on the righter side. This error is called a velocity error.
To compensate this velocity error, it is suggested to provide, for example, between the memory control circuit 20 and the phase controller 23 in FIG. 2 with a circuit shown in FIG. 3. In this configuration a clock signal is supplied from the phase control circuit 23 to contact a of a switching circuit 27 and also to phase shifters 31 to 38. The phase shifters 31 to 38 are set in a range of from phase .pi./2 to phase 4.pi. at steps of .pi./2. With this, a switching control circuit 26 controls the switching circuit 27, based on the period between horizontal synchronizing signals obtained by a clock generator 24 and a measuring circuit 25, i.e. the frequency of the horizontal synchronizing signal, so that the number of interline write clock pulses of the reproduced video signal can be, for example, 910 by sequentially switching the contacts with contact e as a center.
However, since the write clock signal supplied from the switching circuit 27 performs phase switching in a range of .+-.2.pi. with 2.pi. as a center, in some cases where the components of time base fluctuation of the reproduced video signal to be applied is large, its time base error could not be well compensated.
Moreover, to obtain many phase delays of .pi./2 to 4.pi., a number of phase shifters are required, and in turn involves a problem of complicated control of them.